Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since such devices were first introduced several decades ago. Integrated circuits (ICs) have generally followed “Moore's Law,” which means that the number of devices which will fit on a single integrated circuit chip doubles every two years. Today's IC fabrication facilities are routinely producing 65 nm (0.065 μm) feature size devices, and future fabs soon will be producing devices having even smaller feature sizes.
Commonly used and critical processes employed in fabs include dry plasma etching, reactive ion etching, and ion milling techniques. These techniques were developed in order to overcome numerous limitations associated with chemical etching of semiconductor wafers. Plasma etching, in particular, allows a vertical etch rate to be made much greater than a corresponding horizontal etch rate so that a resulting aspect ratio of the etched features can be adequately controlled.
During the plasma etching process, a plasma is formed above the masked surface of the wafer by adding large amounts of energy to a gas at relatively low pressure, resulting in an ionized gas. By adjusting the electrical potential of the substrate to be etched, charged species in the plasma can be directed to impinge substantially normally upon the wafer wherein materials in the unmasked regions of the wafer are removed.
The etching process can often be made more effective by using gases that are chemically reactive with the material being etched. Reactive ion etching (RIE) combines energetic etching effects of the plasma with a chemical etching effect of the gas. However, many chemically-active agents have been found to cause excessive electrode wear. The worn electrodes need to be quickly and efficiently replaced in order to maintain high process yields within the fab.
A reactive ion etching system typically consists of an etching chamber with an upper electrode (an anode) and a lower electrode (a cathode) positioned therein. The cathode is negatively biased with respect to the anode and the chamber walls. The wafer to be etched is covered by a suitable mask and placed directly on the cathode (e.g., typically an electrostatic chuck). A chemically reactive gas such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), chlorotrifluoromethane (CCIF3), sulfur hexafluoride (SF6), or mixtures thereof, is combined with oxygen (02), nitrogen (N2), helium (He), or argon (Ar) and introduced into the etching chamber and maintained at a pressure which is typically in the millitorr range.
The upper electrode is typically provided with gas apertures which permit the input gas to be uniformly dispersed through the electrode into the chamber. The electric field established between the anode and the cathode dissociates the reactive gas, thus forming a plasma. The surface of the wafer is etched by chemical interaction with the active ions and by momentum transfer of the ions striking unmasked portions of the wafer. The electric field created by the electrodes will attract the ions to the cathode, causing the ions to strike the wafer in a predominantly vertical direction so that the process produces well-defined vertically etched side walls.
With reference to FIG. 1, a typical prior art showerhead electrode assembly 100 for a single wafer etcher is used in which a wafer is supported and spaced one to two centimeters below a silicon electrode 101. An upper surface of the outer edge of the silicon electrode 101 is metallurgically bonded by, for example, silicone or an indium or indium alloy solder to a graphite supporting ring 109. The silicon electrode 101 is a planar disk having uniform thickness from center to edge thereof. The silicon electrode 101 may also take other forms, such as an annular ring. An outer flange on the graphite supporting ring 109 is clamped by an aluminum clamping ring 113 to an aluminum support member 105. The aluminum support member 105 has a peripheral water cooling channel 111. A plasma confinement ring 107 comprised of a Teflon® support ring 107A and an annular Vespel® insert 107B surrounds the outer periphery of the silicon electrode 101.
The purpose and function of the plasma confinement ring 107 is to increase the electrical resistance between the walls of the reaction chamber and the plasma, thereby confining the plasma more directly between the upper and lower electrodes. The aluminum clamping ring 113 is attached to the aluminum support member 105 by a plurality of circumferentially spaced-apart stainless steel bolts threaded into the aluminum support member 105. The plasma confinement ring 107 is attached to the aluminum clamping ring 113 by a plurality of circumferentially spaced-apart bolts threaded into the aluminum clamping ring 113. A radially inwardly-extending flange of the aluminum clamping ring 113 engages the outer flange of the graphite support ring 109. Thus, no clamping pressure is applied directly against the exposed surface of the silicon electrode 101.
Process gas is supplied to the silicon electrode 101 through a central hole 115 in the aluminum support member 105. The process gas is then dispersed through one or more vertically spaced apart baffle plates 103 and passes through gas dispersion holes (not shown) in the silicon electrode 101 to evenly disperse the process gas into the reaction chamber (i.e., the reaction chamber is immediately below the silicon electrode 101).
In order to provide enhanced heat conduction between the graphite support ring 109 and the aluminum support member 105, part of the process gas is supplied through a first gas passage orifice 119 to fill a small annular groove in the aluminum support member 105. In addition, a second gas passage orifice 117 in the plasma confinement ring 107 permits pressure to be monitored in the reaction chamber. To maintain process gas under pressure between the aluminum support member 105 and the graphite support ring 109, a first O-ring seal 121 is provided between a radially inner surface of the graphite support ring 109 and a radially outer surface of the aluminum support member 105. A second O-ring seal 123 is provided between an outer part of an upper surface of the graphite support ring 109 and a lower surface of the aluminum support member 105.
A difficult and time-consuming prior art process of bonding the silicon electrode 101 to the graphite support ring 109 requires heating the silicon electrode 101 to a bonding temperature which may cause bowing or cracking of the electrode 101 due to the different thermal coefficients of expansion of the silicon electrode 101 and the graphite support ring 109. Also, contamination of wafers could result from solder particles or vaporized solder contaminants deriving from the joint between the silicon electrode 101 and the graphite support ring 109 or from the ring itself. The problem with such particulates or other contaminants becomes far more pronounced with sub-65 nanometer design rules employed in contemporaneous IC designs.
In the silicon electrode 101 bonding process, the temperature of the electrode 101 may even become high enough to melt the solder and cause either part or the entire electrode 101 to separate from the graphite support ring 109. However, even if the silicon electrode 101 becomes only partly separated from the graphite support ring 109, local variations in electrical and thermal power transmission between the graphite support ring 109 and the silicon electrode 101 could result in a non-uniform plasma density beneath the electrode 101.
Therefore, what is needed is an efficient means of mounting an electrode to a support or backing ring that is simple, robust, and cost-effective. Also, the mounting means must account for any induced stresses due to thermal coefficient differences between the electrode and the support member.